Optimal n-tier multilevel interconnect architectures for gigascaleintegration (GSI)

摘要

A multilevel interconnect architecture design methodology thatnoptimizes the interconnect cross-sectional dimensions of each metalnlayer is introduced that reduces logic macrocell area, cycle time, powernconsumption or number of metal layers. The predictive capability of thisnmethodology, which is based on a stochastic wiring distribution,nprovides insight into defining the process technology parameters forncurrent and future generations of microprocessors andnapplication-specific integrated circuits (ASICs). Using this methodologynon an ASIC logic macrocell case study for the 100 nm technologyngeneration, the optimized n-tier multilevel interconnect architecturenreduces macrocell area by 32%, cycle time by 16% or number of wiringntracks required on the topmost tier by 62% compared to a conventionalndesign where pitches are doubled for every successive pair of levels. Annew repeater insertion methodology is also described that furthernenhances gigascale integration (GSI) system performance. By usingnrepeaters, a further reduction of 70% in macrocell area, 18% in cyclentime, 25% in number of metal levels or 44% in power dissipation isnachieved, when compared to an n-tier design without repeaters. The keyndistinguishing feature of the methodology is its comprehensive frameworknthat simultaneously solves two distinct problems-optimal wire sizing andnwiring layer assignment-using independent constraints on maximumnrepeater area for efficient design space exploration to optimize thenarea, power, frequency, and metal levels of a GSI logic megacell