Cell-based layout techniques supporting gate-level voltage scalingfor low power

摘要

Gate-level voltage scaling is an approach that allows differentnsupply voltages for different gates in order to achieve power reduction.nPrevious research focused on determining the voltage level for each gatenand ascertaining the power saving capability of the approach vianlogic-level power estimation. In this correspondence, we presentncell-based layout techniques that make the approach feasible. We firstnpropose a new block layout style and a placement strategy to support thenvoltage scaling with conventional standard cell libraries. Then, wenpropose a new cell layout style with built-in multiple supply rails sonthat gate-level voltage scaling can be immediately embedded in a typicalncell-based design flow. Experimental results show that proposedntechniques maintain good power benefit while introducing moderate layoutnoverhead