Technology mapping for high-performance static CMOS and passtransistor logic designs

摘要

Two new techniques for mapping circuits are proposed in thisnpaper. The first method, called the odd-level transistor replacementn(OTR) method, has a goal that is similar to that of technology mapping,nbut without the restriction of a fixed library size and maps a circuitnto a virtual library of complex static CMOS gates. The second technique,nthe static CMOS/pass transistor logic (PTL) method, uses a mix of staticnCMOS and PTL to realize the circuit and utilizes the relation betweennPTL and binary decision diagrams. The methods are very efficient and cannhandle all of the ISCAS'85 benchmark circuits in minutes. A comparisonnof the results with traditional technology mapping using SIS onndifferent libraries shows an average delay reduction above 18% for OTR,nand an average delay reduction above 35% for the static CMOS/PTL method,nwith significant savings in the area