首页> 中文期刊> 《电子器件》 >DOE技术在低电压CMOS晶体管中的质量控制∗

DOE技术在低电压CMOS晶体管中的质量控制∗

         

摘要

采用DOE( Design of Experiment)试验方法进行了CMOS晶体管工艺流片的分卡操作,研究18个样品的Vt 区注入Dvt、N场注入DNF、TEMP注入DP 这3种注入剂量变化的情形下阈值电压Vtn和Vtp的调控优化值。通过最大跨导法测试阈值电压Vtn和Vtp ,考查3种注入剂量对Vtn和Vtp的影响趋势,发现Dvt和DNF直接决定Vtn ,Dvt和DP 直接决定Vtp。结果表明,Vtn为0.082 V~0.600 V,关系式为 Vtn=0.15791Dvt+0.12320DNF+0.11433;Vtp为0.0535 V~0.6300 V,关系式为 V2tp=-0.03077D2vt-0.01688D2P+0.71899。%Based on the DOE(Design of Experiment)method and process splits of CMOS transistor,the threshold voltages of Vtn and Vtp of 18 CMOS samples were modulated by changing the implanting doses and doping concentra-tions of 3 process parameters:Dvt doses,N field implant doses DNF ,and TEMP implant doses DP . Subsequently,we tested the threshold voltage Vtn and Vtp by means of maximum transconductance method,then analysed the effects of process parameters on Vtn and Vtp. It indicated that Dvt and DNF directly determine Vtn,Dvt and DP also directly deter-mine Vtp. The results showed that Vtn was 0.082 V~0.600 V,the relationship was Vtn=0.15791Dvt+0.12320DNF+0. 11433;Vtp was 0.0535 V~0.6300 V,and V2tp=-0.03077D2vt-0.01688 D2P+0.71899.

著录项

相似文献

  • 中文文献
  • 外文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号