Delay fault testing of IP-based designs via symbolic path modeling

摘要

Predesigned blocks called intellectual property (IP) cores arenincreasingly used for complex system-on-a-chip (SoC) designs. Thenimplementation details of IP cores are often unknown or unavailable, sondelay testing of such designs is difficult. We propose a method that canntest paths traversing both IP cores and user-defined blocks, annincreasingly important but little-studied problem. It modelsnrepresentative paths in IP circuits using an efficient form of binaryndecision diagram (BDD) and generates test vectors from the BDD model. Wenalso present a partitioning technique, which reduces the BDD size bynorders of magnitude and makes the proposed method practical for largendesigns. Experimental results are presented that show that it robustlyntests selected paths without using extra logic and, at the same time,nprotects the intellectual contents of IP cores