Method and system for identifying tested path delay faults

摘要

The present invention relates to a method and system for identifying tested path-delay faults in integrated circuits. A path status graph is generated to represent the detected status of simulated path-delay faults. The path status graph includes vertices representing primary inputs, primary outputs and elements of the circuit. Detected status path-delay faults can be dynamically distributed to edges of the path status graph. Tested path-delay faults can be identified from traversal of the edges of the path status graph.