An on-chip march pattern generator for testing embedded memorycores

摘要

In this correspondence, we propose an effective approach tonintegrate 40 existing march algorithms into an embedded low hardwarenoverhead test pattern generator to test the various kinds ofnword-oriented memory cores. Each march algorithm is characterized bynseveral sets of up/down address orders, read/write signals, read/writendata, and lengths of read/write operations. These characteristics arenstored on chip so that any desired march algorithm can be generated withnvery little external control. An efficient procedure to reduce thenmemory storage for these characteristics is presented. We use only twonprogrammable cyclic shift registers to generate the various read/writensignals and data within the steps of the algorithms. Therefore, thenproposed pattern generator is capable of generating any march algorithmnwith small area overhead