Evaluating power consumption of parameterized cache and busarchitectures in system-on-a-chip designs

摘要

Architectures with parameterizable cache and bus can support largentradeoffs between performance and power. We provide simulation datanshowing the large tradeoffs by such an architecture for severalnapplications and demonstrating that the cache and bus should benconfigured simultaneously to find the optimal solutions. Furthermore, wendescribe analytical techniques for speeding up the cache/bus power andnperformance evaluation by several orders of magnitude over simulation,nwhile maintaining sufficient accuracy with respect to simulation-basednapproaches