Design and analysis of a dynamically reconfigurablethree-dimensional FPGA

摘要

This paper presents the design and analysis of a dynamicallynreconfigurable field programmable gate array (FPGA) that consists ofnthree physical layers: routing and logic block layer, routing layer, andnmemory layer. The architecture was developed using a methodology thatnexamines different architectural parameters and how they affectndifferent performance criteria such as speed, area, and reconfigurationntime. The resulting architecture has high performance while thenrequirement of balancing the areas of its constituent layers isnsatisfied