首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
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Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

机译:采用混合CMOS逻辑样式的用于深亚微米设计的稳健,节能全加器设计

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We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full ad-nders
机译:我们提出了一种采用混合CMOS设计风格的1-b全加法器的新设计。对深亚微米实现良好的可驱动性,噪声稳健性和低能耗操作的追求指导了我们的研究,以探索混合CMOS样式设计。混合CMOS设计风格利用各种CMOS逻辑风格电路来构建具有所需性能的新型全加法器。这为设计人员提供了更高的设计自由度,以针对广泛的应用,从而显着减少了设计工作量。我们还将混合CMOS全加法器根据其结构分为三大类。使用这种分类,可以构想许多全加器设计。我们将介绍属于提议类别之一的新全加器设计。新的全加法器基于新颖的xor-xnor电路,可同时生成xor和xnor全摆幅输出。该电路的性能优于同类电路,功率延迟产品(PDP)改善了5%-37%。还提出了一种新颖的混合CMOS输出级,该级利用同时的xor-xnor信号。该输出级提供了良好的驱动能力,可以级联加法器,而无需在级联级之间插入缓冲器。与最佳同类产品相比,PDP减少了约40%。在我们的实验过程中,我们发现许多先前报道的加法器在低电源电压下工作时会遭受低摆幅和高噪声的问题。拟议的全加器具有高能效,并且在不折衷驱动能力和可靠性的情况下优于几个标准的全加器。新的全加法器电路可在低压下成功运行,并具有出色的信号完整性和驱动能力。为了评估新的全加法器在实际电路中的性能,我们将其嵌入到带有最终进位-传播加法器的4位和8位,4操作数进位保存阵列加法器中。与标准完整添加程序相比,新添加程序显示出更好的性能

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