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Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign

机译:借助系统互连优化的高效封装引脚排列规划,以实现封装板协同设计

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In conventional package design, engineers designate the ball grid array (BGA) pin-out manually, this always postpones the time-to-market (TTM) of products due to the turn-around between package and design houses. Recent papers propose a method of automatically generating the pin-out and taking signal integrity (SI), power delivery integrity (PI), and routability (RA) into account simultaneously by pin-block design and floorplanning, thus dramatically speeding up the developing time. However, this approach ignores the considerations of shorter path length and equilength/length matching in routing printed circuit board (PCB) trace and pin-out assignment for high-speed interface IP designs, such as USB and PCI Express. Since these features are the most important performance metrics during chip-package-board codesign, in this paper we propose the ideas to optimize the system interconnects during package pin-out design. These ideas keep the same minimized package size as aforementioned recent work and ensure that SI, PI, and RA can still be considered with significant reduction in design cost. It is achieved by relaxing the restriction of pin-block side and order on the package, usually specified by package designers. The experimental results on industrial chipset design cases show that the average improvement of our pin-block planner is over 40% when comparing the design cost with the previous work, among which we have one case accommodated over a thousand pins. Our ideas also work for any kind of pin-block or pin-group configurations.
机译:在传统的包装设计中,工程师手动指定球栅阵列(BGA)引脚,由于包装和设计公司之间的周转,这总是会推迟产品的上市时间(TTM)。最近的论文提出了一种自动生成引脚输出并通过引脚块设计和布局来同时考虑信号完整性(SI),功率传输完整性(PI)和可布线性(RA)的方法,从而大大加快了开发时间。但是,这种方法忽略了对于高速接口IP设计(例如USB和PCI Express)的布线印刷电路板(PCB)布线和引脚分配中较短路径长度和等长/长度匹配的考虑。由于这些功能是芯片封装板代码签名期间最重要的性能指标,因此在本文中,我们提出了在封装引脚分配设计期间优化系统互连的想法。这些想法保持了与上述最新工作相同的最小化封装尺寸,并确保仍可以考虑采用SI,PI和RA,同时大幅降低了设计成本。它是通过放松通常在封装设计人员中指定的对引脚座侧面和封装顺序的限制来实现的。工业芯片组设计案例的实验结果表明,与以前的工作相比,我们的引脚块规划器的平均改进率超过40%,其中一个案例容纳了上千个引脚。我们的想法也适用于任何类型的引脚块或引脚组配置。

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