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A Nonbinary LDPC Decoder Architecture With Adaptive Message Control

机译:具有自适应消息控制的非二进制LDPC解码器架构

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A new decoder architecture for nonbinary low-density parity-check (LDPC) codes is presented in this paper to reduce the hardware operational complexity in VLSI implementations. The low decoding complexity is achieved by employing adaptive message control (AMC) that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. To implement the proposed AMC, we develop the architecture of a horizontal sequential nonbinary LDPC decoder. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.
机译:本文提出了一种用于非二进制低密度奇偶校验(LDPC)码的新型解码器架构,以降低VLSI实现中的硬件操作复杂性。低解码复杂度是通过采用自适应消息控制(AMC)来实现的,该消息可以动态修整信念信息的消息长度以减少内存访问和算术运算的数量。为了实现所提出的AMC,我们开发了水平顺序非二进制LDPC解码器的体系结构。设计架构中的关键组件时考虑了可变的消息长度,以利用建议的AMC的优势。仿真结果表明,与现有工作相比,所提出的非二进制LDPC解码器体系结构可以显着减少硬件操作和功耗,并且性能下降可忽略不计。

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