A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS

摘要

A 10-Gb/s on-chip 1-D eye-opening monitor (EOM) for receiver front-end equalizer boost gain adaptations is presented. The proposed EOM circuits report in real-time horizontal eye-openings using equalizer output by calculating the probability density of the waveform in the central row of pixels of the eye diagram. In addition, a novel multi-phase generator circuit with a delay gain calibration is also demonstrated. It is suitable for EOM circuits to generate a multi-phase sampling clock. The proposed 1-D-EOM circuit is included in a 10-Gb/s receiver design to verify its adaptation functions, and the circuit is implemented using the 65-nm CMOS technology. The sampling phase resolution is 1.5625 ps (where the time for one bit is 100 ps, with a total of 64 phases), and the response time is $64 similar tomu ext{s}$ . The total power consumption of the EOM circuit is 1.5 mW with a 1-V supply voltage, and the circuit occupies a layout area of 60 $mu ext{m},,imes $ 450 $mu ext{m}$ . The results show that the reported horizontal eye-opening value is proportional to the value from a real eye diagram monitor from the test buffer.