Combined CMOS decision feedback equalizer and clock data recovery circuit design in broadband receivers.

摘要

With ever increasing high-speed link rates, the transmission path bandwidth becomes severely limited by the dielectric loss, skin effect and impedance discontinuities of the copper cable and interconnects. To design robust, high-performance broadband receivers, advanced equalization techniques are required to remove the intersymbol interference (ISI) due to these loss mechanisms. Because of the better noise performance, decision feedback equalizers (DFE) are preferred to analog equalizers.; The clock data recovery (CDR) circuit has always been the most critical part of broadband receivers. There are stringent requirements on the jitter performance of the CDR, including low jitter peaking, high jitter tolerance, and sufficient long run length.; Because of the advantages of low power dissipation and better integration capability, CMOS technology has been widely used. On the other hand, a typical CMOS process has lower transistor fT, lower intrinsic gain gm, and higher 1/f noise than a typical bipolar transistor process. At speeds up to 10Gb/s, the performance of 0.18mum CMOS process becomes marginal. To improve the speed of CMOS circuits, bandwidth enhancement techniques need be employed.; To address the above challenges in designing high-speed, low-power, high-performance broadband receivers, an 11.75Gb/s combined DFE and CDR circuit using 0.18mum CMOS process is presented in this dissertation. In the combined DFE and CDR circuit, a three-tap DFE is designed to equalize NRZ data transmitted over coaxial cables. A binary CDR employing a modified Alexander phase detector (PD) is designed to recover the clock from the equalized data. The CDR employs an LC VCO to generate the full-rate clock. In order to reduce the power consumption and sensitivity to temperature and fabrication variations, the feedback path of the DFE is merged with the Alexander PD of the CDR. The chip is tested with an 11.75Gb/s 231 - 1 PRBS input data over a cable with 12.0dB attenuation at the 5.875GHz Nyquist frequency. The measured RMS random jitter of the recovered clock is 2.15ps. The measured RMS random jitter of the retimed data is 4.96ps. The jitter bandwidth is measured to be 12MHz. The jitter tolerance is within the SONET specification. The power consumption of the test chip is 216mW.