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340-GHz Low-Cost and High-Gain On-Chip Higher Order Mode Dielectric Resonator Antenna for THz Applications

机译:太赫兹应用的340GHz低成本,高增益片上高阶模介电谐振天线

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A low-cost and high-gain on-chip terahertz (THz) dielectric resonator antenna (DRA) is proposed in this work. The DRA consists of a low-loss dielectric resonator (DR) made of high-resistivity silicon material and an on-chip feeding patch realized in a 0.18-μm CMOS technology for exciting the desired electromagnetic (EM) mode. The DR can be easily fabricated to the required dimension by wafer dicing of a 2-in silicon wafer. With a 500-μm thick DR, a higher order mode of TEδ,1,7 can be excited, which greatly enhances the antenna gain. Such higher order mode operation also provides a reliable design. If a fundamental mode is selected, the DR thickness is around 100 μm at THz frequencies, which not only requires an additional wafer thinning process, but the wafer is also easily broken during the fabrication process. The feeding patch is used to excite the TEδ,1,7 mode. Moreover, its ground plane also prevents the EM field from leaking into the lossy CMOS silicon substrate, which improves the antenna efficiency. The simulated antenna gain can be 7.9 dBi while providing radiation efficiency of 74% at 341 GHz with 7.3% bandwidth. To characterize the DRA performance, an identical CMOS imager is designed to be integrated with the proposed DRA and an on-chip patch antenna. By comparing the measured responsivity of these two imagers, the gain improvement of the DRA over the on-chip patch antenna can be obtained. Three samples are measured to evaluate the robustness of the proposed antenna over process variation. The measured results show that the maximum gain improvement of 6.7 dB can be acquired at 327 GHz. The proposed DRA with the integrated CMOS imager is also employed to successfully demonstrate a THz transmissive imaging system at 327 GHz. To the best of authors’ knowledge, this is first higher order mode DRA working at THz frequencies.
机译:在这项工作中,提出了一种低成本,高增益的片上太赫兹(THz)电介质谐振器天线(DRA)。 DRA包括一个由高电阻率硅材料制成的低损耗介电共振器(DR)和一个片上馈电贴片,该芯片通过0.18μmCMOS技术实现,用于激发所需的电磁(EM)模式。通过2英寸硅晶圆的晶圆切割,可以轻松将DR制成所需的尺寸。使用500μm厚的DR,可以激发更高阶的TEδ,1,7模式,从而大大提高了天线增益。这样的高阶模式操作还提供了可靠的设计。如果选择基本模式,则在THz频率下DR厚度约为100μm,这不仅需要额外的晶圆减薄工艺,而且在制造过程中晶圆也容易破碎。补片用于激发TEδ,1,7模式。此外,其接地平面还可以防止EM场泄漏到有损CMOS硅基板中,从而提高了天线效率。模拟天线增益可以为7.9 dBi,同时在341 GHz频率下提供7.3%带宽的74%的辐射效率。为了表征DRA性能,将相同的CMOS成像器设计为与建议的DRA和片上贴片天线集成在一起。通过比较这两个成像器的测量响应度,可以获得DRA在片上贴片天线上的增益提高。测量了三个样本,以评估所提出的天线在过程变化中的鲁棒性。测量结果表明,在327 GHz频率下可获得6.7 dB的最大增益提高。带有集成CMOS成像器的建议DRA也被用于成功演示327 GHz的THz透射成像系统。据作者所知,这是第一个工作在THz频率的高阶模式DRA。

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