机译:具有侧壁间隔物图案的单电子晶体管
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Republic of Korea;
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Republic of Korea;
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Republic of Korea;
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Republic of Korea;
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Republic of Korea;
Sidewall spacer patterning; Single-electron transistor; DGSET; MOSET; Phase control; Sidewall depletion gate; Multi-valued logic; Complementary self-biasing method; SPICE;
机译:独立的双门鳍Fin SONOS闪存,采用侧壁间隔物图案制作
机译:通过模式依赖氧化在绝缘体上硅结构上制造的太赫兹超快单电子晶体管
机译:侧壁限定绝缘体上硅单电子晶体管的制备与表征
机译:具有侧壁耗尽栅的硅单电子晶体管及其在动态单电子晶体管逻辑中的应用
机译:将选择性硅外延与薄的侧壁隔离层集成在一起,用于亚微米级的高源/漏MOSFET。
机译:超疏水生物传感晶体管的几何图案可实现生物混合物的时空解析
机译:具有侧壁耗尽栅极的硅单电子晶体管及其在动态单电子晶体管逻辑中的应用
机译:用于金纳米粒子选择性沉积的二氧化硅基板的化学图案化及单电子晶体管的制作