Effect of thin gate dielectrics and gate materials on simulated device characteristics of 3D double gate JNT

摘要

In this paper a novel Silicon based three dimensional (3D) double-gate Junctionless Nanowire Transistor (JNT) of 20 nm gate length is proposed. The device characteristics such as gate characteristics and drain characteristics are studied with the help of Sentaurus TCAD by using different gate materials such as Al, Ti, n~+ Polysilicon, Au and using different ultra thin gate dielectrics such as SiO_2, Si_3N_4 and HfO_2. The effect of various work functions and dielectrics on the threshold voltage of the JNT is also analysed. From the TCAD simulation results it is observed that high-K material (HfO_2) as gate dielectric shows better drain characteristics with respect to others. The JNT with Al as gate material gives better current characteristics with respect to others. It is also analysed that under flat-band condition the driving of drain current does not directly depend on the gate-oxide capacitance but depends upon the channel doping concentrations. Thus by choosing the proper gate material and gate dielectric combinations, the desired device characteristics could be obtained for JNT.