Gate-Material-Engineered Junctionless Nanowire Transistor (JNT) With Vacuum Gate Dielectric for Enhanced Hot-Carrier Reliability

摘要

This paper reports the physics-based drain-current model for the gate-material-engineered vacuum junctionless nanowire transistor for improved hot-carrier reliability and analog/ RF applications. The novel structure is based upon asymmetric gate oxide by combining the Al2O3 gate dielectric at the source side and the vacuum dielectric at the drain side, which significantly reduces the band-to-band tunneling effect, electric field, and drain-induced gate leakage. However, the vacuum dielectric enhances the immunity against the hot carriers' induced damage, but it has the deficiency of having a low drive current, transconductance, and therefore low Ion/Ioff current ratio. Therefore, gate material engineering is incorporated to make the device suitable for improved analog/RF applications. The analytical results are verified by the ATLAS TCAD device simulator.