Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

摘要

In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 µF improvement with Hafnium Oxide (Hfo_2) than Silicon Oxide (S1O_2). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO_2 than S1O_2. It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO_2 than S1O2.