A circuit concept for reducing soft error in high-speed memory cells

摘要

For bipolar static memory cells, the essence of the circuit concept is that the potential at the common-emitter node of the cross-coupled transistors (flip-flop) should be allowed to swing freely. This can be implemented by decoupling the common-emitter node from the heavily capacitively loaded lower-word line, e.g. by inserting a current source or a current mirror between the two. The predicted improvements of Q/sub CRIT/, soft-error rate, and the experimental results are presented.