A circuit concept for reducing soft-error in high-speed memory cells

摘要

This paper describes a circuit concept for reducing the soft error of high-speed flip-flop type memory cells. For bipolar static memory cells, the essence of the concept is that the potential at the common-emitter node of the cross-coupled transistors (flip-flop) should be allowed to swing freely. This can be implemented by decoupling the common-emitter node from the heavily-capacitively-loaded lower-word line, for example, by inserting a current source or a current mirror between the two. The predicted improvement of QCK1T, soft-error rate, and the experimental results are presented.