Ultra shallow P+/N junctions using plasma immersion ion implantation and laser annealing for sub 0.1 mu m CMOS devices

摘要

Classical beam line ion implantation is limited to low energies and cannot achieve P+/N junctions requested for < 45 nm ITRS node. RTA (rapid thermal annealing) needs to be improved for dopants activation and damage reductions. Spike annealing process also induces a large diffusion mainly due to TED (transient enhanced diffusion).Compared to conventional beam line ion implantation limited to a minimum energy implantation of 200 eV, plasma immersion ion implantation ((PIII)) is an emerging technique to get ultimate shallow profiles (as-implanted) due to no lower limitation of energy and high dose rate. On the another hand, laser thermal processing (LTP) allows to obtain very shallow junction with no TED, abrupt profile and activated depth control.In this paper, we show the implementation of the BF3 PIII associated with the LTP. Ions from BF3+ plasma have been implanted in 200 mm n-type silicon wafers with energies from 100 eV to 1 keV and doses from 3E14 to 5E15 at/cm(2) using PULSION (R) (IBS PIII prototype). Then, wafers have been annealed using SOPRA VEL 15 XeCI excimer lasers (l = 308 nm, 200 ns, 15 J/pulse) with energy density from 1 to 2.5 J/cm(2) and 1, 3 or 10 shots. The samples have been characterized at CEA LETI by secondary ion mass spectrometry (SIMS) combined with four points probe sheet resistance measurements. (c) 2005 Elsevier B.V. All rights reserved.