Extraction of the trap distribution responsible for SILCs in MOS structures from measurements and simulations of DC and noise properties

摘要

In this paper we present a detailed investigation of the properties of SILCs through MOS capacitors, focusing our attention on the extraction of the trap distribution from DC and shot noise properties of the structure. Our model of SILCs, based on inelastic Trap-Assisted Tunneling, is able to reproduce both the J-V characteristics and the shot noise suppression, explaining the latter in terms of Pauli Exclusion Principle and Coulomb repulsion. Fitting of numerical results with J-V characteristics before and after stress led to the extraction of distributions of native traps and stress-induced traps, respectively. In order to extract a unique trap distribution, comparison with shot noise measurements revealed to be mandatory. The combined effect of the two types of traps explains the DC and noise properties for the range of oxide thickness comprised between 4 nm and 10 nm, in which SILCs play a dominant role.