Stress investigation of annular-trench-isolated TSV by polarized Raman spectroscopy measurement and finite element simulation

摘要

As a 3D integration technology, the through silicon via (TSV) has attracted increasing interest owing to the need for reducing energy consumption in devices. However, high thermal stress is induced owing to large mismatches in the coefficients of thermal expansion (CTE) between the copper via and the silicon (Si) substrate in TSVs, causing critical reliability issues such as the performance degradation of stress-sensitive devices. We proposed a novel structure, the annular-trench-isolated (ATI) TSV, as a possible solution for the reliability issues caused by thermal stress in 3D packaging technology with TSVs. The ATI TSV structure has an extra Si ring outside of the metal core. We successfully fabricated an All TSV with a 10-mu m diameter using separate etching processes for the insulator trench and the metal core. A narrow insulator trench with a thickness of 2 mu m was formed, and its aspect ratio (AR) was as high as 10. A Si ring with a thickness of 1 mu m remained between the insulator layer and the metal core. In order to study the stress level of the ATI TSV, we investigated the radial and axial thermal stresses using polarized Raman spectroscopy and a simulation by the Finite Element Method. Agreement between the simulation results and the measured stress data was observed and validated the simulation model. Furthermore, we revealed that the Si substrate of the All TSV had a lower thermal stress level than the regular TSV. This was accomplished using the validated simulation model owing to the redistribution of stress by the Si ring in the ATI TSV.