机译:一种68nW新型CMOS子带隙电压基准电路
Huazhong Univ Sci & Technol, Sch Opt & Elect Informat, Wuhan Int Inst Microelect, Wuhan 430074, Hubei, Peoples R China;
Huazhong Univ Sci & Technol, Sch Opt & Elect Informat, Wuhan Int Inst Microelect, Wuhan 430074, Hubei, Peoples R China;
Huazhong Univ Sci & Technol, Sch Opt & Elect Informat, Wuhan Int Inst Microelect, Wuhan 430074, Hubei, Peoples R China;
CMOS; Subthreshold circuit; Energy efficient circuit; Low supply voltage; Process-insensitive; Temperature compensation;
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机译:在90nm CMOS中实现低压子带隙电压参考