Analysis of interface trap density of metal-oxide-semiconductor devices with Pr_2O_3 gate dielectric using conductance method

摘要

In this study, the interface trap density of metal-oxide-semiconductor (MOS) devices with Pr_2O_3 gate dielectric deposited on Si is determined by using a conductance method. In order to determine the exact value of the interface trap density, the series resistance is estimated directly from the impedance spectra of the MOS devices. Subsequently, the dispersion characteristics are numerically analyzed on the basis of a statistical model. Lastly, the process-dependent interface trap density of Pr_2O_3 is evaluated. It is concluded that high-pressure annealing and a superior quality interfacial SiO_2 layer are of crucial importance for achieving a sufficiently low interface trap density.