...
首页> 外文期刊>Japanese Journal of Applied Physics. Part 2, Letters & Express Letters >Improved Conductance Method for Determining Interface Trap Density of Metal-Oxide-Semiconductor Device with High Series Resistance
【24h】

Improved Conductance Method for Determining Interface Trap Density of Metal-Oxide-Semiconductor Device with High Series Resistance

机译:确定高串联电阻的金属氧化物半导体器件界面陷阱密度的改进电导方法

获取原文
获取原文并翻译 | 示例
           

摘要

The existence of series resistance in metal-oxide-semiconductor (MOS) devices can result in both the degradation of capacitance at a high frequency and the decrease in conductance. Using a conventional conductance method that does not consider the series resistance, the interface trap density can be underestimated. We propose an improved conductance method based on an equivalent circuit model including the series resistance. Compared with the conventional method, this new method enables the accurate determination of interface trap density.
机译:金属氧化物半导体(MOS)器件中存在串联电阻会导致高频下的电容下降和电导率下降。使用不考虑串联电阻的常规电导方法,可能会低估界面陷阱密度。我们提出了一种基于包括串联电阻在内的等效电路模型的改进电导方法。与传统方法相比,此新方法可以准确确定界面陷阱密度。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号