Impact of interfacial trap states on achieving bias stability in polymer field-effect transistors

摘要

Low operational stability and undesirable shift of electrical properties at ambient conditions are the major barriers in the commercialization of organic field-effect transistors (OFETs). In this study, we report an improvement in operational stability of solution-processable polymer Poly[2,5-(2-octyldodecyl)-3,6-diketopyrrolopyrrole-alt-5,5-(2,5-di(thien-2-yethieno[3,2-b]thiophene)] (DPPDTT) based OFETs by applying bias stress for short times. Two types of devices were fabricated using i) bare Si3N4 as gate dielectric that offers higher interfacial traps and ii) using an additional layer of PMMA along with Si3N4 that offers lower interfacial traps. The OFET with PMMA layer shows better performance i.e. threshold voltage around 15 V, mobility similar to 0.2 cm(2) /V.s and current on/off ratio in the range of 10(6). The bias stress measurements show the initial decrease in the performance parameters in both devices. However, the device with lower traps shows a smaller decrease in the performance parameters and achieves a stable performance when devices are put under continuous gate bias stress, while the high trap state device continued to degrade. The reported results provide a route to achieve good stability in the electrical performance of OFETs in ambient conditions.