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A Novel Current-Controlled Oscillator-Based Low- Supply-Voltage Microbolometer Readout Architecture

机译:基于电流控制的基于电流控制的振荡器的低电源电压微频计读数架构

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摘要

In this paper, we present a novel, almost-digital approach for bolometer readout circuits to overcome the area and power dissipation bottlenecks of analog-based classical microbolometer circuits. A current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) is utilized instead of a capacitive transimpedance amplifier (CTIA) in the classical readout circuits. This approach, which has not been reported before, both produces the required gain in the bolometer input circuit and directly digitizes the bolometer signal. With the proposed architecture, the need for large capacitances (of the order of 10-15 pF for each column) at which the current is accumulated in the bolometer circuits and the voltage headroom limitation of classical microbolometer circuits are eliminated. Therefore, the proposed architecture permits to design readout circuits with reduced pixel pitch and lower power supply, both of which in turn lead to higher-resolution Focal Plane Arrays (FPAs) with lower power dissipation. The new architecture is modeled and simulated using a 180-nm CMOS process for sensitivity, noise performance, and power dissipation. Unlike the 3.3-V power supply usage of classical readout circuits, the proposed design utilizes 1.2-V analog and 0.9-V digital supply voltages with a power dissipation of almost half of the classical approach.
机译:在本文中,我们提出了一种新颖的,几乎数字方法,用于提高计读数电路,以克服基于模拟的古代微电位器电路的区域和功耗瓶颈。利用电流控制的振荡器(CCO)基础的模数转换器(ADC)代替经典读出电路中的电容式跨阻抗放大器(CTIA)。这种方法之前尚未报道,两者都在提高计输入电路中产生所需的增益,并直接数字化提高计信号。利用所提出的架构,消除了对电流累积在大计电路中累积电流的大电容(每列的10-15PF的顺序)以及经典微倍频器电路的电压余量限制。因此,所提出的体系结构允许设计具有降低的像素间距和较低电源的读出电路,两者又导致具有较低功耗的更高分辨率的焦平面阵列(FPAS)。使用180nm CMOS工艺进行建模和模拟新架构,用于灵敏度,噪声性能和功耗。与经典读数电路的3.3V电源使用不同,所提出的设计利用1.2V模拟和0.9V数字电源电压,电源耗散几乎一半的经典方法。

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