An Adaptively Biased Capacitor-Less Low Dropout Regulator with Improved Transient Performance

摘要

A novel fully on-chip low dropout (LDO) linear regulator with a supply voltage of 1.6 V, dropout voltage of 200 mV and a quiescent current of 64.4 mu A is presented in this paper. The slew rate limitations of conventional low dropout regulator (LDR) employing folded cascode structure are overcome by fixed bias LDR (FB LDR) with the usage of recycled transistors of conventional LDR. The FB LDR with its limited input common mode range limits the transient response. The adaptive bias LDR (AB LDR) overcomes these limitations of FB LDR and further enhances the transient performance. However, fast rise and fall time demands of advanced digital technology demand the regulator to respond to corresponding fast load changes. These challenges are addressed by an additional fast reacting path. An undershoot of 89.95 mV for a load current changes from 0 mA to 100 mA and an overshoot of 150.1 mV for a current change of 100-0 mA is observed for the adaptive bias transient enhanced LDR. The load regulation of 20.6 mu V/mA and power supply rejection (PSR) of -47.8 dB@ 10 kHz is achieved due to the improved closed loop gain and bandwidth of LDR. The standard 180 nm UMC CMOS process is employed.