Analysis, Design, and Performance Evaluation of a Dynamically Slew Enhanced Adaptively Biased Capacitor-Less Low Dropout Regulator

摘要

Dynamically slew enhanced adaptive bias (DSE-AB) scheme has been recently introduced for an externally compensated (with-capacitor) regulator for achieving a very fast transient response. The combined effects of enhanced slew rate and expanded loop bandwidth using the DSE-AB scheme produce a very low undershoot and overshoot. When this scheme is directly applied to an internally compensated, capacitor-less low dropout regulator (CL-LDR) topology, besides the slew enhancement, the instantaneous dynamic current may reduce the damping factor momentarily and produce more ringing in the load transient response. This paper first analyzes the generation of momentary low damping factor in the CL-LDR that uses the DSE-AB scheme. A current limited DSE-AB scheme is also proposed to increase the momentary damping factor for minimizing the ringing in the settling behavior. To validate the proposed scheme, the CL-LDR is implemented in a 0.18$ mu$m CMOS technology and the regulator's performance is evaluated in different dynamic conditions. Experimental result shows an undershoot of 45 mV during 0-100-mA load step and an overshoot of 25 mV during the other edge.