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首页> 外文期刊>Journal of Applied Physics >Electron holography analysis of a shallow junction for planar-bulk metal-oxide-semiconductor field-effect transistors approaching the scaling limit
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Electron holography analysis of a shallow junction for planar-bulk metal-oxide-semiconductor field-effect transistors approaching the scaling limit

机译:接近体积极限的平面体金属氧化物半导体场效应晶体管浅结的电子全息分析

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摘要

We investigated electrostatic potential distributions in source/drain extensions (SDEs) in metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated using state-of-the-art junction formation technology. We first demonstrate that electron holography can directly reveal potential distribution in scaled MOSFETs when specimen preparation artifacts are reduced, which we did by using back side low-energy Ar ion milling. Second, we examine the potential distributions in SDEs in a scaled (30-nm-gate-length) MOSFET fabricated by using a combination of cluster B implantation, millisecond annealing, and multihalo implantation. The results show that these junction formation technologies enable fabrication of very abrupt and shallow (10-nm-deep) SDE junctions. In addition, our experimental analysis, in conjunction with a Monte Carlo doping-process simulation, indicates that B channeling along the <110> direction of the Si substrate during the implantation process significantly blurs the SD junction profiles and that multihalo implantation can increase junction abruptness. Third, we show that our experimental results describe well the roll-off characteristics of the MOSFETs.
机译:我们研究了使用最新结形成技术制造的金属氧化物半导体场效应晶体管(MOSFET)的源/漏扩展区(SDE)中的静电势分布。我们首先证明,当减少样品制备伪影时,电子全息图可以直接显示按比例MOSFET的电位分布,这是通过使用背面低能Ar离子铣削完成的。其次,我们研究了通过使用簇B注入,毫秒退火和多卤注入的组合制造的按比例缩放(栅长为30 nm)的MOSFET中SDE中的电势分布。结果表明,这些结形成技术能够制造非常突然和浅的(10 nm深)SDE结。此外,我们的实验分析结合蒙特卡罗掺杂工艺仿真表明,在注入过程中沿Si衬底的<110>方向沟道的B沟道显着模糊了SD结的轮廓,多卤注入会增加结的突变性。第三,我们表明我们的实验结果很好地描述了MOSFET的滚降特性。

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