Advanced 10nm Width Silicon-on-lnsulator Tri-Gate Transistors with NO Annealing of Gate Oxide Using Optimized Novel Silicon-on-lnsulator Realization Technology

摘要

An advanced method of the novel silicon-on-insulator (SOI) realization technology is proposed for the fabrication of SOI trl-gate transistors. Using the new method, 10nm width SOI tri-gate transistors are successfully fabricated on standard Si bulk wafers, and result in excellent electrical characteristics after optimizing the processing parameters. Among others, low-cost and high manufacturability to fabricate SOI tri-gate transistors are advantages of the proposed method. Formed on the standard Si bulk wafer process, the SOI tri-gate transistors with gate length (L_G) of 45 nm have reasonable threshold voltage (V_(TH)) of 0.18V and showed the enhanced current drivabllity up to 20%. They also demonstrated good short channel effect immunities: sub-threshold swing (SS) and drain induced barrier lowering (DIBL) were 70mV/dec and 24mV/V, respectively. Therefore, the novel method for the novel SOI realization technology proposed in this work will be one of the candidates for the scaling-down strategy in the future.