Double gate and tri-gate transistor formed on a bulk susbtrate and method for forming the transistor

• 1. 形成在体衬底上的双栅极与三栅极晶体管及形成该晶体管的方法 [P] . 中国专利： CN102077353B . 2014.06.18
• 2. 形成在体衬底上的双栅极与三栅极晶体管及形成该晶体管的方法 [P] . 中国专利： CN102077353A . 2011-05-25
• 3. DOUBLE GATE AND TRI-GATE TRANSISTOR FORMED ON A BULK SUBSTRATE AND METHOD FOR FORMING THE TRANSISTOR [P] . 韩国专利： KR101630387B1 . 2016-06-24

  机译： 在大块基体上制成的双闸极和三闸极晶体管及其形成方法

• 4. Method for forming a double gate and tri-gate transistor and the transistor formed on a bulk substrate [P] . 日本专利： JP5679970B2 . 2015-03-04

  机译： 形成双栅极和三栅极晶体管的方法以及在体衬底上形成的晶体管

• 5. Double gate and tri-gate transistor formed on a bulk substrate and method for forming the transistor [P] . 英国专利： GB2491512B . 2013-02-13

  机译： 在块状基板上形成的双栅极和三栅极晶体管及其形成方法

• 1. Effect of grain boundary on electric performance of ZnO nanowire transistor with wrap-around gate [J] . ZHOU Yu-ming, HE Yi-gang 中南大学学报（英文版） . 2011,第004期
• 2. Double-gate tunnel field-effect transistor: Gate threshold voltage modeling and extraction [J] . LI Yu-chen, ZHANG He-ming, HU Hui-yong, 中南大学学报（英文版） . 2014,第002期
• 3. Impact of Using Double-Patterning Versus Single-Patterning on Threshold Voltage $(V_{rm TH})$ Variation in Quasi-Planar Tri-Gate Bulk MOSFETs [J] . Shin C., Park I.J. Electron Device Letters, IEEE . 2013,第5期
• 4. 3D Modelling and Performance Analysis of Dual Material Tri-Gate Tunnel Field Effect Transistor [J] . Saha Priyanka, Sarkhel Saheli, Sarkar Subir Kumar IETE Technical Review . 2019,第2期
• 5. 3D Modelling and Performance Analysis of Dual Material Tri-Gate Tunnel Field Effect Transistor [J] . Saha Priyanka, Sarkhel Saheli, Sarkar Subir Kumar IETE Technical Review . 2019,第2期
• 6. A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products [C] . Jan C.-H., Al-amoody F., Chang H.-Y., Symposium on VLSI Technology . 2015
• 7. Enhancement of the Dynamic Performance of Electrolyte-Gated Transistors: Toward Fast-Switching, Low-Operating Voltage Printed Electronics [D] . Zare Bidoky, Fazel. 2019
• 8. Analytical modeling of uniaxial strain effects on the performance of double-gate graphene nanoribbon field-effect transistors [O] . George S Kliros 2014
• 9. A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors [O] . 2016
• 10. Numerical Simulation of the Comparative Electrical Performance of the PermeableBase Transistor, Opposed Gate-Source Transistor and Heterostructure Launched Ballistic Field Effect Transistor [R] . Grubin, H. L., Kreskovsky, J. P., Meyyappan, M., 1990

• 1. Effect of grain boundary on electric performance of ZnO nanowire transistor with wrap-around gate [J] . 周郁明 ,何怡刚 . 中南大学学报 . 2011,第004期
• 2. Study of short-term synaptic plasticity in Ion-Gel gated graphene electric-double-layer synaptic transistors [J] . Chenrong Gong ,Lin Chen ,Weihua Liu . 半导体学报：英文版 . 2021,第1期
• 3. Double-gate tunnel field-effect transistor：Gate threshold voltage modeling and extraction [J] . 李妤晨 ,张鹤鸣 ,胡辉勇 . 中南大学学报 . 2014,第002期
• 4. 双栅极氢闸流管高压快脉冲源研究 [C] . 王欣 ,唐丹 ,邓君 . 全国第五届核仪器及其应用学术会议 . 2005
• 5. 双栅极空气计数器电子控制与接口电路设计研究 [A] . 何格夫 . 2005