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High-uniformity centimeter-wide Si etching method for MEMS devices with large opening elements

机译:用于具有大开口元件的MEMS器件的高度均匀的厘米级Si蚀刻方法

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摘要

We propose a compensated mesh pattern filling method to achieve highly uniform wafer depth etching (over hundreds of microns) with a large-area opening (over centimeter). The mesh opening diameter is gradually changed between the center and the edge of a large etching area. Using such a design, the etching depth distribution depending on sidewall distance (known as the local loading effect) inversely compensates for the over-centimeter-scale etching depth distribution, known as the global or within-die(chip)-scale loading effect. Only a single DRIE with test structure patterns provides a micro-electromechanical systems (MEMS) designer with the etched depth dependence on the mesh opening size as well as on the distance from the chip edge, and the designer only has to set the opening size so as to obtain a uniform etching depth over the entire chip. This method is useful when process optimization cannot be performed, such as in the cases of using standard conditions for a foundry service and of short turn-around-time prototyping. To demonstrate, a large MEMS mirror that needed over 1 cm(2) of backside etching was successfully fabricated using as-is-provided DRIE conditions. (C) 2018 The Japan Society of Applied Physics.
机译:我们提出了一种补偿网格图案填充方法,以实现具有大面积开口(超过厘米)的高度均匀的晶圆深度蚀刻(超过数百微米)。网孔的开口直径在大蚀刻区域的中心和边缘之间逐渐变化。使用这样的设计,取决于侧壁距离的蚀刻深度分布(称为局部加载效应)反向补偿了超过厘米级的蚀刻深度分布,称为全局或裸片(芯片)级加载效应。只有具有测试结构图案的单个DRIE可以为微机电系统(MEMS)设计人员提供蚀刻深度,该深度取决于网孔尺寸以及与芯片边缘的距离,而设计人员只需设置孔尺寸即可以在整个芯片上获得均匀的蚀刻深度。当无法执行过程优化时,例如在为铸造服务使用标准条件且周转时间原型很短的情况下,此方法很有用。为了演示,使用原样提供的DRIE条件成功地制造了需要超过1 cm(2)背面蚀刻的大型MEMS反射镜。 (C)2018年日本应用物理学会。

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  • 来源
    《Japanese journal of applied physics》 |2018年第4s期|04FC03.1-04FC03.7|共7页
  • 作者单位

    Univ Tokyo, Dept Elect Engn & Informat Syst, Bunkyo Ku, Tokyo 1130034, Japan;

    Univ Tokyo, Dept Elect Engn & Informat Syst, Bunkyo Ku, Tokyo 1130034, Japan;

    Univ Tokyo, Dept Elect Engn & Informat Syst, Bunkyo Ku, Tokyo 1130034, Japan;

    Sony Corp, Compound Semicond Dev Dept, Device Technol Dev Div, Device & Mat R&D Grp,R&DPF, Atsugi, Kanagawa 2430013, Japan;

    Sony Corp, Compound Semicond Dev Dept, Device Technol Dev Div, Device & Mat R&D Grp,R&DPF, Atsugi, Kanagawa 2430013, Japan;

    Univ Tokyo, Inst Ind Sci, CNRS, LIMMS,Meguro Ku, Tokyo 1538505, Japan;

    Univ Tokyo, Dept Elect Engn & Informat Syst, Bunkyo Ku, Tokyo 1130034, Japan;

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