Nanoscale shielded channel dual gate stack silicon on nothing junctionless transistor for improving short channel effect and analog performance

摘要

A nanoscale shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) is proposed in this paper. The simulation results are compared with single material gate silicon on insulator junctionless transistor (SMGSOIJLT) and shielded channel silicon on insulator junctionless transistor (SCSOIJLT), along with the study of different parameters for different side gate lengths of SCDGSSONJLT. This paper demonstrates on double layer gate stack effect on shielded channel silicon on nothing junctionless transistor. It is seen that high-k dielectric material of gate insulator decreases off state current in subthreshold region. The result shows that high I_(on)/I_(off) ratio (10~7) improve transconductance, very less threshold voltage variation, very less band to band tunnelling current and very less DIBL of SCDGSSONJLT. Transconductance of SCDGSSON JLT is greater by 40% as compared to SCSOIJLT. The G_M/I_D value of SCDGSSONJLT is 60% larger than SMGSOIJLT in subthreshold region. Subthreshold swing is below 70 mV/decade of SCDGSSONJLT when side gate length is 40 nm. It has been observed that there is 47% reduction in subthreshold swing of SCDGSSONJLT as compared to SCSOIJLT. The effect of different side gate and main gate length are studied.