Delay fault models for VLSI circuits

摘要

State-of-the-art technologies for VLSI circuits give rise to various defect mechanisms that may cause a circuit to fail when operated at its designated speed of operation. Such defects are conventionally modeled by delay faults. In this paper, we review delay fault models used for circuits described at the gate level. The shortcomings of these models in accommodating physical phenomena that determine the worst-case delay of a circuit, and in modeling physical defects, were described in several works. We review methods proposed recently to address these shortcomings at the gate level, and describe a new approach based on a generalized fault model.