Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits

摘要

Delay test in nano-scale VLSI circuits becomes more difficult with shrinkingtechnology feature sizes and rising clock frequencies. In this dissertation, we study threechallenging issues in delay test: fault modeling, variational delay evaluation and pathselection under process variation. Previous research of fault modeling on resistive spotdefects, such as resistive opens and bridges in the interconnect, and resistive shorts indevices, lacked an accurate fault model. As a result it was difficult to perform faultsimulation and select the best vectors. Conventional methods to compute variational delayunder process variation are either slow or inaccurate. On the problem of path selectionunder process variation, previous approaches either choose too many paths, or missed thepath that is necessary to be tested.We present new solutions in this dissertation. A new fault model that clearly andcomprehensively expresses the relationship between electrical behaviors and resistivespots is proposed. Then the effect of process variations on path delays is modeled with alinear function and a fast method to compute coefficients of the linear function is alsoderived. Finally, we present the new path pruning algorithms that efficiently prune unimportant paths for test, and as a result we select as few as possible paths for test whilethe fault coverage is satisfied. The experimental results show that the new solutions areefficient and accurate.