A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits

摘要

A continuous-time waveform monitoring technique for quality on-chip power noise measurements features matched probing performance among a variety of voltage domains of interest in a VLSI circuit, covering digital Vdd, analog Vdd, as well as at Vss, and multiple probing capability at various locations on power planes. A calibration flow eliminates the offset as well as gain errors among probing channels. The consistency of waveforms acquired by the proposed continuous-time monitoring and sampled-time precise digitization techniques is ensured. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with ±200 mV at 2.5 V, 1.0 V, and 0.0 V, respectively, with less than 4 mV deviation among 240 probing channels.