首页>
外国专利>
TECHNIQUES AND CIRCUITS FOR ON-CHIP JITTER AND PHASE NOISE MEASUREMENT IN A DIGITAL TEST ENVIRONMENT
TECHNIQUES AND CIRCUITS FOR ON-CHIP JITTER AND PHASE NOISE MEASUREMENT IN A DIGITAL TEST ENVIRONMENT
展开▼
机译:数字测试环境中片上抖动和相位噪声测量的技术和电路
展开▼
页面导航
摘要
著录项
相似文献
摘要
Proposed digital on-chip jitter and phase noise measurement techniques and circuits are presented and include the use of a digitally controlled delay locked loop having very fine resolution but limited range to track the phase error between the tested device output clock and its reference clock. Some implementations employ a combination of a high-gain 1-bit phase detector, a digital accumulator and a fine digitally controlled delay element to track the accumulated phase difference between the reference clock and the device under test. Observing the accumulator output is an indication of the jitter and performing a Fast Fourier Transform of the accumulator output provides the phase noise of the device under test.
展开▼