Measurement and characterization of multilayered interconnectcapacitance for deep-submicron VLSI technology

摘要

This paper presents the measurement and characterization ofnmultilayered interconnect capacitances for a 0.35-Μm CMOS logicntechnology, which become a critical circuit limitation to highnperformance VLSI design. To measure multilayered capacitances ofnnonstacked, stacked, and orthogonally crossing interconnect lines, newntest structures and measurement methods are presented. The measuredninterconnect capacitances were employed to evaluate and calibrate TCADntools for the simulation of high-speed interconnect technologies. Thisnstudy shows that the calibration method considerably improves thenaccuracy of simulation results compared with measured results