Test structure for measurement of multilayered interconnect capacitance for VLSI technology

摘要

Structure for testing multilayer integrated circuits, where each layer has its own conducting tracks. The test structure comprises an ammeter (7) connected between a power input (8) and an earth (6) and at least two circuit branches. Circuit breakers (9,11) are arranged so that the capacitance between two circuit tracks (1,2) can be determined. The first branch comprises a first breaker (9) between the ammeter and a first track (1), and the second branch has a similar arrangement of breaker between ammeter and second track (2).