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机译:HKMG多鳍块式FinFET器件中的源/漏串联电阻提取
Department of Electrical EngineeringParallel and Scientific Computing Laboratory, Institute of Communications Engineering, National Chiao Tung University, Hsinchu, Taiwan;
Conductivity; Electrical resistance measurement; FinFETs; Layout; Logic gates; Resistance; Semiconductor device measurement; Bulk FinFET; Bulk fin-type field effect transistor (FinFET); Channel fin doping; Contact size; Epi growth; Explicit model; Extraction; High-κ/metal gate; Measurement; Multi fins; Series resistance; Source/Drain resistance; Test structure; channel fin doping; contact size; epi growth; explicit model; extraction; high-k/metal gate; measurement; multifins; series resistance; source/drain (S/D) resistance; test structure;
机译:在HKMG体FinFET器件中沿(110)和(100)方向对SiGe表面粗糙度进行迁移模型提取
机译:16nm栅极FinFET器件中源漏串联电阻的确定
机译:降低Si / sub 1-x / Ge / sub x / source / drain的源/漏串联电阻及其对PMOS晶体管器件性能的影响
机译:识别源排水泄漏的根本原因导致高级散装FinFET设备的软盘
机译:用于降低纳米级FinFET的源极漏极电阻的先进技术。
机译:随机离散掺杂剂引起的具有固定顶鳍宽度的16nm栅极梯形体FinFET器件的电特性波动
机译:考虑到3D电流流动的FinFET寄生源/漏极电阻的建模