Optimization on Layout Style of Diode Stackup for On-Chip ESD Protection

摘要

The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than ${rm V}_{rm DD}$ or lower than ${rm V}_{rm SS}$. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.