3-D Integration and ESD Protection: Design and Analysis

摘要

A set of design of experiments matrix was created to evaluate the possibilities of electrostatic-discharge (ESD) failures during the complex 3-D integration process as a function of the ESD protection level. A detailed set of pass/fail criteria based on circuit performance was established. Various phases of 3-D integration are monitored for ESD failures. Based on measured samples, it was observed that the functionality test and leakage test show circuit performance degradation and a larger fail rate after chip-to-chip bonding on designs without ESD protection.