首页> 外文会议>Electrical Overstress/Electrostatic Discharge Symposium >3D integration ESD protection design and analysis
【24h】

3D integration ESD protection design and analysis

机译:3D集成ESD保护设计与分析

获取原文

摘要

A Design of Experiments (DOEs) matrix was created to evaluate probability of fails during a complex 3D integration process as a function of ESD protection level. A detailed set of pass/fail criteria based on circuit performance was established. Based on measured samples, functionality test and leakage test show circuit performance degradation and larger fail rate after chip bonding on designs without ESD protection.
机译:创建了实验设计(DOE)矩阵,以评估复杂3D集成过程中的故障可能性,作为ESD保护级别的函数。建立了基于电路性能的一组详细的通过/失败标准。根据测得的样本,功能测试和泄漏测试表明,在没有ESD保护的设计上进行芯片键合后,电路性能会下降并且故障率更高。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号