The problem of design for testability of gate-level dividers is investigated using the single stuck-at fault model. Two C-testable designs are given for the nonrestoring array divider. The first design is C-testable with only eight vectors. The additional hardware required to obtain C-testability for an n*n nonrestoring array divider consists of n-1 two-input XOR gates and one control input. The second design does not require any extra circuitry or control inputs, and is C-testable with six vectors. In other words, the basic array structure itself is C-testable. Two easily testable designs for the restoring array divider are also presented. The first n*n array design is shown to be linearly testable with 2n+8 vectors. In the second design, a logic implementation that makes the design C-testable with only six vectors is used. The extra circuitry required for both designs consists of n XOR gates and one control input.
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