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Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

机译:异步电路的综合,以实现固定式和鲁棒的路径延迟故障可测试性

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摘要

In this paper, we present methods for synthesizing multilevel asynchronous circuits to be both hazard free and completely testable. Making an asynchronous two-level circuit hazard free usually requires the introduction of either redundant or nonprime cubes or both. This adversely affects the circuit's testability. However, using extra inputs, which is seldom necessary, and a synthesis-for-testability method, we convert the two-level circuit into a multilevel circuit that is completely testable. To avoid the addition of extra inputs as much as possible, we introduce new exact minimization algorithms for hazard-free two-level logic where we first minimize the number of redundant cubes and then minimize the number of nonprime cubes. We target both the stuck-at and robust path delay fault models using similar methods. However, the area overhead for the latter may be slightly higher than for the former.
机译:在本文中,我们提出了无危险且可完全测试的多级异步电路的合成方法。要使异步两级电路无危险,通常需要引入冗余或非主要的多维数据集,或同时引入这两者。这不利地影响了电路的可测试性。然而,使用很少需要的额外输入和可测试性综合方法,我们将两级电路转换为完全可测试的多级电路。为了尽可能避免增加额外的输入,我们针对无危害的两级逻辑引入了新的精确最小化算法,在该算法中,我们首先最小化冗余多维数据集的数量,然后最小化非主要多维数据集的数量。我们使用类似的方法来针对固定和鲁棒的路径延迟故障模型。但是,后者的面积开销可能会比前者稍高。

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