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Optimal clock period clustering for sequential circuits with retiming

机译:具有重定时功能的时序电路的最佳时钟周期聚类

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In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock period. Current algorithms address combinational circuits only, and treat a sequential circuit as a special case, by removing all flip-flops (FF's) and clustering the combinational part of the sequential circuit. This approach breaks the signal dependencies and assumes the positions of FF's are fixed. The positions of the FF's in a sequential circuit are in fact dynamic, because of retiming. As a result, current algorithms can only consider a small portion of the whole solution space. In this paper, we present a clustering algorithm that does not segment circuits by removing FF's. In additional, it considers the effect of retiming. The algorithm can produce clustering solutions with the optimal clock period under the unit delay model. For the general delay model, it can produce clustering solutions with a clock period provably close to optimal.
机译:在本文中,为了最小化时钟周期,我们考虑了对时序电路进行群集的问题,该时序电路受每个群集区域的约束。当前的算法仅处理组合电路,并且通过移除所有触发器(FF)并聚集顺序电路的组合部分,将顺序电路作为一种特殊情况。这种方法打破了信号依赖性,并假设FF的位置是固定的。实际上,由于重定时,FF在顺序电路中的位置实际上是动态的。结果,当前算法只能考虑整个解决方案空间的一小部分。在本文中,我们提出了一种聚类算法,该算法不能通过去除FF来分割电路。此外,它还考虑了重定时的影响。该算法可以在单位延迟模型下产生具有最佳时钟周期的聚类解。对于一般的延迟模型,它可以产生时钟周期可证明接近最佳值的聚类解决方案。

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