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Covering conditions and algorithms for the synthesis of speed-independent circuits

机译:速度无关电路综合的覆盖条件和算法

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This paper presents theory and algorithms for the synthesis of standard C-implementations of speed-independent circuits. These implementations are block-level circuits which may consist of atomic gates to perform complex functions in order to ensure hazard freedom. First, we present Boolean covering conditions that guarantee that the standard C-implementations operate correctly. Then, we present two algorithms that produce optimal solutions to the covering problem. The first algorithm is always applicable, but does not complete on large circuits. The second algorithm, motivated by our observation that our covering problem can often be solved with a single cube, finds the optimal single-cube solution when such a solution exists. When applicable, the second algorithm is dramatically more efficient than the first, more general algorithm. We present results for benchmark specifications which indicate that our single-cube algorithm is applicable on most benchmark circuits and reduces run times by over an order of magnitude. The block-level circuits generated by our algorithms are a good starting point for tools that perform technology mapping to obtain gate-level speed-independent circuits.
机译:本文介绍了与速度无关的电路的标准C实现综合的理论和算法。这些实现是块级电路,可以由原子门组成,以执行复杂的功能,以确保危害的自由。首先,我们介绍布尔值覆盖条件,以确保标准C实现正确运行。然后,我们提出了两种产生覆盖问题的最佳解决方案的算法。第一种算法始终适用,但不能在大型电路上完成。第二种算法是根据我们的观察结果得出的,即我们的覆盖问题通常可以用单个多维数据集解决,因此,当存在这样的解决方案时,它会找到最佳的单个多维数据集解决方案。当适用时,第二种算法比第一种更通用的算法有效得多。我们提供了基准规范的结果,这些结果表明我们的单立方体算法适用于大多数基准电路,并且将运行时间缩短了一个数量级。由我们的算法生成的块级电路是执行技术映射以获得门级速度独立电路的工具的良好起点。

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